Electrical & electronics
Circuit design, PCB development, embedded systems, control and practical testing. My primary focus for graduate roles.
View engineering workShakes Wang / Electronics & Computer Science
I’m Shakes Wang, an MEng Electronics & Computer Science graduate from the University of Edinburgh. I’m seeking graduate opportunities in electrical and electronics engineering, with strengths in data analysis, structured problem-solving and technical communication.
A clear starting point
Start with my engineering work, then explore the analytical and people skills I bring to a team.
Browse all projects ↗Circuit design, PCB development, embedded systems, control and practical testing. My primary focus for graduate roles.
View engineering workPython, R and MATLAB applied to research, modelling and machine learning. Turning complex evidence into findings that can be explained.
View analytical workRequirements analysis, engineering context and peer-learning leadership. Experience relevant to technical and analytical consulting.
Explore consulting skills01 / Selected work
Electrical and electronics projects lead the selection below, followed by data analysis, research and software. Use the filters to go straight to the work most relevant to you.
Original assembled PCB · AMSL3 report
From photodiode current to a tested PCB. Circuit calculations, simulation, schematic capture, breadboard prototyping and soldered assembly.
Altium Designer / LTspice / Bench testing
Designed the receiver chain and audio path, selected components and developed the schematic and PCB. Used continuity checks to locate shorts during assembly.
Worked through transimpedance amplification, DC blocking, Sallen–Key filtering and gain stages. Compared a 4.7 MHz breadboard cut-off with the 6.9 MHz PCB result; both were within the required range.
Original board photograph shown above. The schematic and measured frequency response below come from my AMSL3 laboratory report. These are laboratory measurements, not commercial product specifications.
Convert photodiode current into a useful electrical signal while controlling bandwidth and providing an audio output. The receiver required a 3–8 MHz cut-off; the audio path provided a separate listening check.
Calculated component values for the transimpedance amplifier, DC blocker, active filters and gain stage. Prototyped before moving to PCB, then checked component orientation, solder joints and continuity during bring-up.
The schematic shows the signal chain; the board photograph shows the assembled hardware; the frequency-response plot connects implementation with the bandwidth requirement. Differences between breadboard and PCB measurements motivated discussion of tolerances and parasitic effects.
Original Simulink architecture · assignment report
Designed and evaluated a third-order CRFF modulator for an audio-band ADC, investigating how architecture and non-ideal behaviour affect signal quality.
MATLAB / Simulink / Delta-Sigma Toolbox
Synthesised and scaled loop coefficients, modelled the modulator and assessed SQNR, harmonic distortion, stability, integrator gain and mismatch.
The ideal-case simulation reported 115.4 dB SQNR against a 105 dB target. Non-ideal cases degraded performance. This is a simulation result, not a measurement from a fabricated ADC. The report contains inconsistent dither labels, so no dither setting is assigned to that figure here.
Used a third-order cascade-of-resonators feed-forward architecture with a 3-bit quantiser and OSR of 128. Compared design options and synthesised coefficients with the Delta-Sigma Toolbox before scaling the loop and evaluating the Simulink model.
Examined spectra and signal quality across input conditions, then varied finite integrator gain, loop-coefficient mismatch, DAC mismatch and dither. These experiments distinguish an ideal noise-shaping baseline from sensitivity to implementation non-idealities.
The block diagram explains the chosen architecture. The output spectrum shows the ideal-case noise-shaping behaviour. A strong ideal result does not establish that every non-ideal case meets the target, or that a physical converter would reproduce it.
Identified motor behaviour from measured step responses, compared models with experiments and tuned feedback control.
Transfer functions / PID / Stability analysis
Estimated transfer-function parameters from step-response measurements, investigated frequency response and stability, and applied Ziegler–Nichols tuning followed by practical adjustment.
The lab report describes reducing overshoot below 20% while retaining zero steady-state error. The exercise demonstrated the trade-off between response speed, overshoot and stability in the tested setup.
Used measured step responses to estimate steady-state gain and time constants, then compared an empirical motor model with a model derived from the motor’s physical relationships.
Explored open-loop and closed-loop behaviour, frequency response and stability. Used Ziegler–Nichols methods as an initial tuning point, then adjusted proportional, integral and derivative parameters to manage overshoot and response speed.
The report records reducing proportional gain and increasing derivative time during final adjustment. The response plot below shows the tested setup approaching its setpoint with reduced oscillation; the reported sub-20% overshoot result is specific to that laboratory exercise.

Built a microphone amplifier, digitised audio using an STM32 microcontroller and reconstructed the recorded signal in MATLAB.
LTspice / STM32 / MATLAB / Breadboard testing
Designed the amplifier in LTspice, built it on breadboard, substituted available components and added decoupling, power indication and a measurement path. The microphone signal was digitised by the STM32, transferred as sample values and converted to a waveform and WAV file in MATLAB.
My accompanying STM32 labbook also documents LED duty-cycle experiments, UART communication with a terminal, and conversion of 12-bit ADC samples back into voltage values. These exercises connect firmware configuration with observable outputs and support the later audio-recording work.
Checked DC bias and used a signal generator to investigate gain and cut-off behaviour. Practical component substitutions produced differences from the intended filter response, which the report compared with simulation.
The recording was quiet and its observed duration differed from the expected sample count and rate. The report discusses possible microphone/input-level causes, but does not establish a single confirmed root cause. This is a useful example of connecting analogue measurements with digital-sampling checks.


Investigated combinational and sequential logic through circuit construction, LTspice simulation and waveform analysis.
LTspice / CD4000-series logic / Timing analysis
My digital-systems daybook documents a half-adder using NAND and XOR logic, followed by D-latch, flip-flop and shift-register experiments. Truth tables connect the gate-level circuit with its expected outputs.
Connected four CD4013 flip-flop stages in simulation to a common clock. The recorded outputs show the active bit progressing through 0001 → 0010 → 0100 → 1000 across successive clock periods.

Used clock and data transitions to investigate propagation delay, setup time and hold time. The report compares observations with datasheet values and identifies a discrepancy in the hold-time estimate, considering stimulus settings and manual observation as possible causes.
These figures document discrete-logic circuit simulations. The FPGA and Verilog work is described separately.
Designed, simulated and implemented digital logic in Verilog, applying finite-state machines and timing concepts.
Verilog / FPGA / Finite-state machines
Implemented and tested FPGA-based logic, including an LED-control application, and investigated hardware behaviour while applying digital-system concepts.
Applied digital-logic concepts through simulation and implementation in Verilog, including finite-state machines and timing. Hardware testing helped connect expected logic behaviour with what the FPGA actually did.
A team robotics project connecting two-hand grasp configurations, sampling-based path planning and inverse-dynamics control in simulation.
Python / Pinocchio / NumPy / Meshcat / PyBullet
Move a cube between initial and target poses with a dual-arm robot while accounting for an obstacle. The WANG_ULLAH submission brings together grasp geometry, motion planning, trajectory generation and torque control using the course’s simulation framework.
My teammate and I worked together across the project, jointly developing and debugging the geometry, planning and control stages.
The inverse-geometry routine stacks the two hand-pose errors and Jacobians, uses a pseudoinverse update with a posture-bias term, and projects configurations to joint limits. Collision checks are used while searching for configurations that align both hands with the cube’s hooks.
The RRT-style planner samples cube poses, solves for corresponding grasp configurations and grows a tree through local interpolations. Candidate connections include collision and obstacle-distance checks. A shortcut stage attempts to remove intermediate nodes through checked connections.
The control code densifies the joint path and constructs a Bézier trajectory with position, velocity and acceleration references. Inverse-dynamics tracking is combined with Cartesian spring forces at the grasp points, mapped into joint torques through the hand Jacobians.
The original team screen recording shows the Meshcat planning view, terminal output and PyBullet simulation. The full 76-second sequence is retained at its original speed, including setup and transitions. Silent recording.
Original recording compressed for the web · approximately 1.3 MB · no autoplay.
This is team coursework built on a supplied robotics framework. The recording illustrates the implementation in simulation; it does not establish physical-robot performance or continuous collision clearance after trajectory smoothing.
Investigated longitudinal UK survey data, extending an existing research codebase and connecting data preparation with statistical modelling and interpretation.
R / Data harmonisation / Statistical modelling
Built on supervisor-provided data and base R scripts. Standardised categorical variables, checked missingness, improved visualisations and extended models with sociodemographic predictors.
Extended the work to 14 main-survey waves with spline-based longitudinal analysis and complementary survey-weighted logistic regressions. The two dissertation stages used different survey datasets.
Consistent variable definitions, careful model interpretation and clear attribution matter as much as producing a plot. This overview focuses on methods and contribution; respondent-level survey data is not distributed here.
Worked on consistent coding across waves, categorical-variable definitions, missingness summaries and comparison plots. This preparation was necessary before extending the statistical models or interpreting group differences.
Used spline-based longitudinal analysis to explore changing continuous scores, alongside wave-level survey-weighted logistic regressions for binary caseness. These analyses answer related questions but have different weighting and interpretation requirements.
Compared predicted and observed aggregate trajectories as a diagnostic. Close agreement in a plot is not proof of causation or sufficient validation on its own. Complete-case selection and differences in survey-weight handling remain important limitations.

Extended a team semi-supervised learning baseline with FixMatch training, sample-selection strategies and label-allocation experiments on VisDA-2017.
Python / PyTorch / FixMatch / ResNet-50
I extended the team’s baseline with a FixMatch training pipeline, weak/strong data augmentation and active-sampling strategies. I added label-allocation options, configured experiment sweeps, produced comparison plots and documented how teammates could run the experiments.
A teammate established the initial working SSDA baseline. I built on that foundation; the model, final submission and reported experiment results form part of our group study.
Experiments used a single random seed and limited training duration. Observed rankings are study-specific, rather than evidence that one strategy is universally best.
When only a small fraction of real target images can be labelled, does performance depend more on the training method, the examples selected, the allocation of labels across classes, or the total budget?
Used a ResNet-50 backbone with a bottleneck head. Weakly augmented unlabelled images generated confidence-filtered pseudo-labels, while a strongly augmented view supplied the consistency-training loss. An exponential moving average of model weights was used for evaluation.
Compared random, uncertainty, diversity and hybrid selection; proportional, equal and difficulty-based allocation; and budgets from 0.5% to 5%. The selection figure holds the nominal budget at 1%.
The source-pretrained model provided the selection signal before target adaptation. Rankings could depend on this choice. Experiments used one seed and limited epochs. The baseline and FixMatch training recipes also differ in optimiser and duration, so their comparison does not isolate the loss function alone.


I extended the sampler to control two separate decisions: which images to label, and how many labels to allocate to each class. The implementation supports random, uncertainty, diversity and hybrid selection with proportional, equal or difficulty-based allocation.
I connected strategy, budget and allocation settings to environment-controlled SLURM jobs, organised sweep results and improved plot labels. Cluster-run fixes included checking that scratch-data copies existed before training, so a failed copy would stop clearly instead of failing later.
The three sweeps ask different questions. Selection compares which examples to label; budget varies the total labelled fraction; allocation distributes a fixed budget across classes. Each figure includes training curves and the best observed accuracy from that particular run.


Built application workflows in the first assignment, then developed the PDR motion model in the second stage of a team indoor-positioning project.
Android / Java / Sensor processing



Original screenshots from the team’s User’s Guide. My interface and PDR contributions are distinguished by assignment in the case study below.
In the first assignment I developed the Home, start-location, recording, correction and history/replay workflows. I also contributed manuals, video editing, testing and the demonstration.
In the second assignment I developed the PDR motion prior: validating step events, choosing stride, calibrating the starting heading and generating local east/north increments. Teammates handled the particle-filter fusion, continuing heading-bias correction, map matching and that stage’s UI rendering.
Android hardware step events were debounced and checked against recent acceleration variance before accumulating displacement. Rejecting false stationary steps at this boundary prevents bogus motion from entering the downstream fusion system.
The initial heading depended on two orientation sources being ready. After sensor re-registration, event order could leave calibration incomplete. The documented fix reset the readiness and calibration state and required fresh startup samples.
Compared a Weinberg-style adaptive stride model with fixed-stride steps in local corridor tests, selecting fixed stride for the final implementation. Converted validated stride and heading into local displacement: Δeast = L sin θ and Δnorth = L cos θ. Corridor checks were calibration examples, not general accuracy guarantees.
A 40-second excerpt from the earlier team application’s indoor-positioning screen recording. The marker and green trajectory show the app recording movement on an indoor floor plan. This demonstrates the team application; it does not isolate or benchmark the later PDR module. Silent recording.
Original screen recording · edited to a 40-second excerpt · approximately 1.6 MB. No autoplay.
Connected REST API data, order validation and a weighted A*-style route planner, exporting delivery summaries, movement records and GeoJSON flight paths.
Java / Spring Boot / REST APIs / GeoJSON / Pathfinding
Turn a day’s coursework delivery orders into validated delivery records and planned drone movements. Restaurant menus, orders, no-fly regions and the central area were supplied through REST endpoints.
Separated data retrieval, shared application data, order validation, geometry, route search and output writing. The main application loaded the endpoint data and passed it to the delivery-processing stage.
Implemented checks for payment-field formats and expiry, pizza count, menu membership, a single supplying restaurant, opening day and total price including the delivery charge. Validation codes describe why an order cannot proceed; these are coursework rules rather than a production payment-processing system.
The geometry helper provides coordinate-distance, next-position and polygon-membership operations. The planner expands 16 headings in 22.5° increments, keeps a priority queue of candidate cells and uses parent links to reconstruct a route.
The search score is weighted as f = g + 3h, where g represents accumulated movement cost and h estimates distance to the goal. This prioritises progress toward the goal; it does not establish a globally shortest route. Candidate positions are checked against no-fly polygons.
The delivery stage writes a delivery-summary JSON file, movement-by-movement flight-path records, and a GeoJSON LineString combining the saved route coordinates. The figure uses the 4,791 coordinate entries in a saved coursework output, rather than an invented demonstration path.

The saved output demonstrates route generation and export. It is not a physical-flight recording or independent verification of shortest-path optimality, full obstacle clearance or every order-validation edge case. No new live service call or drone flight was performed to create this portfolio figure.
Worked across parsing, semantic analysis and optimisation in a Python-based ChocoPy compiler framework.
Python / ChocoPy / xDSL
Across three coursework repositories, I worked on parser implementation, type checking, dead-code warnings and optimisation passes. The projects used supplied compiler infrastructure, with my changes recorded in the repository history.
The implementation builds typing environments, checks assignment compatibility and traverses the program structure. A separate visitor tracks variable use to report dead-code conditions, connecting syntax with the meaning and use of program values.
Pattern-rewrite passes fold integer constant expressions, apply selected algebraic simplifications and remove unused literal or binary-expression results. The dead-code pass retains division operations, illustrating why removing an unused result also requires attention to observable behaviour.
Experience reading a larger codebase, traversing syntax trees and expressing transformations over an intermediate representation. The diagram summarises the coursework stages; it is not a performance benchmark or a claim of complete language coverage.
02 / About me
My background combines electronic engineering with software and quantitative analysis. At Edinburgh, I worked across analogue and mixed-signal electronics, embedded systems, digital design, control and instrumentation.
I like working through a problem from modelling to building and testing, discussing ideas with others and learning from what the results reveal. Research and peer-learning roles have also shaped how I check evidence and explain technical ideas.
Altium Designer, LTspice/PSpice, schematic capture, PCB layout, breadboard prototyping, soldering, testing and fault diagnosis.
Verilog, FPGA, finite-state machines, C, STM32 and STM32CubeIDE.
MATLAB/Simulink, Python, R, Java, statistical modelling and data visualisation.
Everyday professional tools
Proficient in Microsoft Office and collaboration tools, alongside LaTeX for technical writing.
03 / A wider perspective
Consulting-relevant experience: defining requirements, evaluating context, explaining evidence and working with others. These academic studies sit alongside my peer-learning and engineering internship experience below.
Systems requirements · Individual coursework
Analysed the external interfaces and operating context of a proposed vaccine-delivery system using PESTLE. Considered infrastructure, cold-chain logistics, stakeholders and information requirements.
A systems requirements exercise, rather than a deployed healthcare service.

Identified stakeholders and external interfaces, then classified requirements by function, performance, operation, environment and cost. This connects proposed technical capabilities with the needs of delivery operators, healthcare workers and communities.
Compared a central drone-distribution concept with motorbike transport, considering remote access, cost, charging, temperature-controlled payloads, security and last-mile handling. The trade-off analysis is a design exercise, not evidence of field deployment.
The diagram connects supply and distribution with monitoring, temperature control, delivery and healthcare hand-off. It makes interfaces and dependencies visible rather than treating the drone as a standalone solution.
Interdisciplinary poster · 2024
Explored AI translation of Chinese online fiction and culturally specific expressions, bringing technical translation evaluation into conversation with reader interpretation.
The poster connects Python/NLTK-based BLEU comparisons with focus-group material and discussion of cultural meaning.
How do AI translations of culturally specific Chinese online-fiction expressions relate to the way readers understand them? The poster brings an engineering evaluation method together with a cultural-communication question.
The poster discusses Python/NLTK-based BLEU comparisons and focus-group material from nine readers in three groups. The quantitative and qualitative elements were used to examine different aspects of translation interpretation.
BLEU measures overlap with a reference translation and is sensitive to the chosen reference. It is not a standalone measure of cultural accuracy. This was a small academic poster study, not a new translation model or broad benchmark.
04 / Experience & education
School of Informatics · University of Edinburgh
Two-year quantitative research project using longitudinal survey data. Extended analysis code, prepared data, evaluated models and communicated methodological choices.
Edinburgh University Students’ Association
Led peer-assisted engineering sessions, explained technical concepts and supported collaborative problem-solving.
China Railway Construction Co., Ltd.
Compared engineering drawings with site conditions, identified discrepancies and supported project documentation.
Edinburgh University Students’ Association
Supported international student engagement and communication through the University’s Global Buddies programme.
University of Edinburgh · Upper 2:1
Study across electronics, computer science, signal analysis, control, instrumentation and embedded systems.
Trinity College · University of Melbourne
GPA 91/100. High Achievement Certificate in History of Ideas (top 3%).
I enjoy dubbing and exploring expression through voice performance.
Driving is another interest of mine. I hold a full UK driving licence.
I write poetry as a personal creative outlet. Halloween is a poem I wrote in November 2020.

Tis the third Halloween that I am taking
Still, I am ruminating
On thy stuff of that girl, that I am whispering
Thousands of sheets were torn, flying
Bunches and bunches of lilies, covering
On thy stuff of my girl, sighing
Last Halloween, thy boy was praying
Thou never present, despairing
Hesitating with little hope, that I was anticipating
Doth my mere fire smother? Or still shing?
God mercy my destiny, letting
Thou arrive here temporarily, smiling
Blown by the wind, frozen,
But smashed by the truth, that I was awaking
Then farewell, my darling
05 / Get in touch
I’m exploring UK graduate roles in electrical and electronics engineering, alongside analytical and technical consulting opportunities. If my skills fit your team, I’d welcome a conversation.